1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a multi-path accessible semiconductor memory device that responds to a virtual row active command to prevent a pre-charge skip for an opened page upon transfer of access authority.
2. Background of the Invention
Generally, a semiconductor memory device having a plurality of access ports is called a multi-port memory device. In particular, a memory device having two access ports is called a dual-port memory device. The dual-port memory device is known in the prior art as an image processing video memory device having a RAM (random access memory) port accessible in a random sequence and a SAM (sequential access memory) port accessible only in a serial sequence.
In addition, a dynamic random access memory (DRAM) device having a shared memory area accessible by multiple processors is herein called a multi-path accessible semiconductor memory device. For example in recent mobile communication systems, electronic devices such as handheld multimedia players, handheld phones, or personal digital assistants (PDAs) each include a multiprocessor system with multiple processors as shown in FIG. 1 for effectively operating with high speed.
FIG. 1 shows a block diagram of a multiprocessor system in a mobile communication device according to the conventional art. The multiprocessor system of FIG. 1 includes a first processor 101 and a second processor 201 connected to each other through a connection line B3. The multiprocessor system of FIG. 1 also includes a first flash memory device 301 and a first DRAM (dynamic random access memory) device 401 coupled to the first processor 101 via a first system bus B1.
The multiprocessor system of FIG. 1 further includes a second DRAM device 402 and a second flash memory device 302 coupled to the second processor 201 via a second system bus B2. The first processor 101 may include applications for data communication or for games, and the second processor 201 may include applications for MODEM functions such as modulation/demodulation of a communication signal.
The flash memory devices 301 and 302 may each be an NOR flash memory device having a NOR structure or a NAND flash memory device having a NAND structure. The NOR or NAND flash memory device is a nonvolatile memory device comprised of an array of memory cells each having a floating gate. The nonvolatile memory device stores data that is not changed even when power is removed. The DRAM devices 401 and 402 are used as main memories for data processing by the corresponding processors 101 and 201.
However in the multi processor system of FIG. 1, each of the processors 101 and 201 is connected to respective DRAM devices 401 and 402. In addition, UART, SPI, or SRAM interfaces operating with relatively low speed are used therein resulting in low data transmission speed. Accordingly, a multiprocessor system of FIG. 2 with just one DRAM device 403 is implemented for increased data transmission speed and reduced sized.
The multiprocessor system of FIG. 2 includes the first processor 101 and the second processor 201 connected to a first flash memory device 303 and a second flash memory device 304, respectively, via system buses B4 and B5, respectively. The multiprocessor system of FIG. 2 also includes the one DRAM device 403 connected to both the first and second processors 101 and 201 via system buses B1 and B2, respectively.
Accordingly in FIG. 2, the one DRAM 403 is accessed by each of the first and second processors 101 and 201 through two different paths, as also disclosed in U.S. Patent Application No. US2003/0093628 to Matter et. al. In such prior art, the one DRAM device 403 includes a memory cell array with first, second, and third portions. The first portion of the memory cell array is accessed only by the first processor 101. The second portion of the memory cell array is accessed only by the second processor 201. The third portion of the memory cell array is a shared memory area accessed by both of the first and second processors 101 and 201.
Mediation is needed for access to the shared memory area by the first and second processors 101 and 201. A UART, SPI or SRAM interface has been used for communication between conventional processors via the system bus B3. However, such an interface operates with limited speed and increased number of pins for three-dimensional games or image communications. Thus, an interface with higher operating speed is desired. Further in FIG. 2, having respective flash memory devices 303 and 304 for each of the processors 101 and 201 may result in complication or increased cost.
Accordingly, a multiprocessor system of FIG. 3 includes first and second processors 100 and 200 that share one DRAM 400 and one flash memory device 300. A data interface between the processors 100 and 200 is implemented through the multi-path accessible DRAM 400. Also in FIG. 3, the first processor 100 is not directly connected to the flash memory device 300 but indirectly accesses the flash memory device 300 through the multi-path accessible DRAM 400.
Each of the processors in FIGS. 2 and 3 may support a page open policy to read or write data from or to the one DRAM device 400. The page open policy has higher data access speed than a page closed policy. For example, when reading data from memory cells connected to a same word line according to the page open policy, the word line is activated only one time, and the bit lines of such memory cells are sensed thereafter.
In contrast for reading such data according to the page closed policy, the word line is re-activated every-time a bit-line is sensed. Thus, additional time for pre-charging the bit lines and re-activating the word line is needed in the page closed policy. Accordingly, recent processors use the page open policy for increased speed for accessing a memory device.
FIG. 4 illustrates a pre-charge skip that occurs upon transfer of access authority according to a page open policy supported by the processors of FIG. 2 or 3. Referring to FIG. 4, a waveform PC indicates commands generated in a page closed policy, and a waveform PO indicates commands generated in a page open policy.
Referring to waveform PC, for reading/writing data from a memory cell connected to an intersection of word line W/L1 and bit line B/L1, a row active command ACT is generated to activate word line W/L1 during a time interval I1. Subsequently, a read/write command R/W is generated to sense or activate bit line B/L1 during time interval I2.
Then for reading/writing data from a memory cell connected to an intersection of the word line W/L1 and bit line B/L2 different from the bit line B/L1, a command PRE to pre-charge the bit line B/L1 is first generated. Thereafter, a row active command ACT to activate the word line W/L1 is then generated. Such pre-charge and row active commands PRE and ACT are applied on the one DRAM 400 or 403 during a time interval A. Subsequently, a read/write command R/W to sense or activate bit line B/L2 is applied on the one DRAM 400 or 403 during a time interval I3.
In contrast referring to the waveform PO in FIG. 4, for reading/writing data from a memory cell connected to an intersection of word line W/L1 and bit line B/L1, a row active command ACT is applied on the one DRAM 400 or 403 to activate word line W/L1 during a time interval T1. Subsequently, a read/write command R/W is applied on the one DRAM 400 or 403 to sense or activate bit line B/L1 during a time interval T2.
For the read mode for example, data is read from the memory cell connected to the intersection of the bit line B/L1 and the word line W/L1 of the one DRAM 400 or 403. Subsequently, in reading/writing data from/to a memory cell connected to an intersection of the word line W/L1 and a bit line B/L2 different from the bit line B/L1, another read/write command R/W is immediately applied to the one DRAM 400 or 403 to sense or activate bit line B/L2. Thus, the pre-charge and row active commands PRE and ACT shown during the time interval A of the waveform PC are omitted in the waveform PO.
Accordingly for the page open policy, the bit lines of memory cells connected to the same word line are sensed or activated with the same word line being maintained to be activated without the time interval A for the page closed policy. Thus, data is accessed with higher speed in the page open policy than in the page closed policy.
When a page is changed in the page open policy, a page close operation should be executed for the opened page when another word line is selected to be activated. However, when authority to access the multi-path accessible DRAM 400 or 403 of FIG. 2 or 3 is transferred from one processor to the other processor (such as at time point to in FIG. 4), a pre-charge operation for bit lines of the shared memory area within the multi-path accessible DRAM 400 or 403 may be skipped with the page open policy.
With such a pre-charge skip, data error may result during a read/write operation performed after the authority transfer. For example, when access authority to the shared memory area of the multi-path accessible DRAM 400 or 403 is transferred from the first processor 100 to the second processor 200 at a time point t0 in FIG. 4, pre-charge of the bit lines B/L1 and B/L2 is skipped.
Subsequently, when the second processor 200 activates another word line and bit line through port B, data error results for the read/write operation. Furthermore, when a bit line is not pre-charged or two word lines are activated simultaneously in a general DRAM, data error results in a read/write operation. Thus, when access authority is to be transferred in a page opened state, the opened page is desired to be closed before the transfer of access authority for preventing data error.